Often integrated circuit blocks are often capable of operating in multiple modes, such as multiple clocking modes, in order to support multiple system-level applications. Typically, when a circuit block operates in a slave clocking mode, a clock signal is input to the circuit block to synchronize its operations with the operations of associated circuit block in the system. During typical master-mode clock operations, a circuit block instead generates the clock signal required to synchronize the operations of a set of associated circuit blocks in the system. In other words, a circuit block operating in a slave-mode receives a controlling signal from another circuit block within the system while the circuit block operating in a master mode generates the controlling clock for transmission to another circuit block within the system.
Clearly, with respects to any circuit block capable of operating in multiple modes, some provision must be made to select the proper mode required by the system application. Currently, mode selection, at either the circuit block or device level, is normally done using one or more dedicated mode select signals. This conventional technique, however, has a number of significant drawbacks. For example, additional circuitry must be provided to both generate and decode the required mode select signals. If these generation and decoding circuits are disposed across circuit block or device boundaries, then additional pads or pins are needed to make the appropriate interconnection. Furthermore, mode select signals generally increase the complexity of the design and the number of factors, which must be considered at the system level.
In sum, a technique is required which allows a multiple-mode capable circuit block or device to be properly configured for correct system-level operation without being subject to the disadvantages of conventional mode selection schemes utilizing dedicated select signals.